Design Verification (DV)

Skills/Experience:
  • Languages: Verilog, System Verilog
  • Methodology: UVM (preferred), OVM, VMM.
  • Knowledge of scripting (Perl, C-shell)
  • SVA will be a plus
  • Good general verification experience with good academy result.
  • Must have:
  • SoC or IP Experience Languages: System Verilog
  • Methodologies: OVM/UVM/VMM DDR/USB/Ethernet/PCIE/Video/HDMI/MIPI/DSI/CSI