#Careers

Careers

Employees can utilize the abundant opportunities that we are providing to exhibit their skills stored within them. We give an Opportunity to learn and lead.


Here are the Opportunities to bring out the best in you -

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we always look for young, passionate, enthusiastic and motivated professionals to be part of our high performing, team-oriented culture.

Experience (years): 2-8 years
Skills/Experience:
1. RTL design experience, familiarity with AHB/AXI buses, experience with spyglass(lint), CDC, core and chip integration

Experience (years): 2-8 years
Skills/Experience:
1. Verilog/VHDL RTL/Conformal Verification(LEC) Synthesis (DC) Spyglass (lint, DFT, PM, CLK/RST)
2. SoC integration flows (integrating multiple IPs and associated, Understanding of Power Management (voltage domain, power domains, clock domains) OCP and AXI protocols ARM understanding
3. Misc.: Debussy, simulators (mti/ncsim), Perl

Experience (years): 2-8 years
Skills/Experience:
1. Languages: Verilog, System Verilog
2. Methodology: UVM (preferred), OVM, VMM.
3. Knowledge of scripting (Perl, C-shell)
4. SVA will be a plus
5. Good general verification experience with good academy result.
Must Have:
6. SoC or IP Experience Languages: System Verilog
7. Methodologies: OVM/UVM/VMM DDR/USB/Ethernet/PCIE/Video/HDMI/MIPI/DSI/CSI

Experience (years) : 2-8 years
Skills/Experience:
1. Strong back ground of ASIC Physical Design: Floor planning, P&R, Extraction, IR Drop Analysis, Static Timing and Signal Integrity.
2. Have some experience on advance Technology: 28nm, 40nm, 45nm, 65nm
3. Hands on experience in cadence or Synopsys tool (Encounter, ICC, PT/PTSI, TEMPUS, DC, RC, VOLTAS)

Experience (years): 2-8 years
Skills/Experience:
1. Should be very strong in Synthesis & Timing concepts
2. Should have knowledge of DC-topo, RTL Compiler or talus
3. Should have handled both block and top level.
4. Should have done both pre and post layout STA

Experience (years): 2-8 years
Skills/Experience:
1. Scan insertion & ATPG using Fastscan/TestKompress /DFTCompiler/DFTMax/DFTAdvisor/TetraMax
2. Pattern Simulation with and without timing annotation & debugging

Job Description:
1. Hands-on responsibility from synthesis to place and route of a complex GPU/CPU block through signoff flows including timing and physical verification.
2. Synthesis, Floor plan, Place & Route in chip-level and hierarchical physical implementation environment.
3. Running MBIST and DFT insertion into block, understanding impact of MBIST/Scan and debug logic is desirable.
4. Interact with RTL counterpart to resolve design issues pertaining to block closure.
5. Ability to work independently to make good technical trade-offs between power, area, and timing. Ability to work well in a team setting and drive critical design issues to closure.
6. Strong scripting/programming skills in Tcl, Perl, Shell, and/or Python is strongly preferred.
7. Synopsys DC/ICC2, Fusion Compiler knowledge is required.
8. Solid understanding of Electrical Engineering fundamentals, analytical aptitude and excellent attention to detail

Job Description:
1. As a Design Verification Engineer you will contribute to the functional verification of GPU Subsystems such as Shader, Texture, and Memory Systems. Responsibilities
2. Triage regression failures and make testbench updates
3. Debug functional errors in RTL model using simulation and debug tools.
4. Maintain efficient and clean regression status
5. Develop Scalable SystemVerilog/UVM testbenches for unit level and/or Cluster level verification.
6. Review Architecture and Micro-Architecture specifications.
7. Closely work with Architects and RTL designers.
8. Define, maintain and execute unit level and/or Cluster level verification testplans.
9. Generate and run Testcases on logic simulation models.
10. Code Functional coverage models and System Verilog assertions.
11. Drive Functional Coverage and Code coverage to closure.
12. Integrate C++ reference model into Scoreboards

Requirements:
1. 5-15 year’s industry experience in a design verification role.
2. Proficient in System Verilog/UVM/OVM, OOP/C++
3. Knowledge of GPU, experience with Shader, Texture, or Memory System a plus
4. Experience with code coverage and functional coverage driven verification methodology.
5. Experience in creating, running and debugging of SystemVerilog/UVM constraint-random Testbench.
6. Excellent working knowledge of scripting languages such as Python or Perl.
7. Understanding of micro-architecture, logic design, FSMs, arithmetic datapath pipelines.
8. Strong functional verification experience including Test planning, Testbench Architecture, Test/Coverage Model/Assertion Development.
9. Strong debugging skills
10. Strong programming skills with good understanding of algorithms and data structures
11. Good verbal and written communication skills.

Job Description:
As a DFT, you will work with chip architects, chip designers, implementation engineers and test engineers to define the DFT and DFD (Design for Debug) architecture, implementation, and test plans for both mixed-signal and digital VLSI designs. Then you’ll ensure it becomes reality. We’re doing a grounds-up implementation of new chip architecture, so you’ll have to ability to affect a new design.

Minimum qualifications:
1. BA/BS degree in Electrical/Computer Engineering with 5+ years of practical experience
2. Strong fundamentals in digital ASIC design; experience using Verilog or VHDL
3. Experience with ASIC test, DFT, and debug
4. 5+ years of practical experience with test or DFT
5. Preferred qualifications
6. Experience using the Tessent tools
7. Hands-on expertise with commercial test generation tools for large complex designs
8. Strong fundamental knowledge of DFT techniques include JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, scan compression, IEEE 1500 Standard, and MBIST, LBIST
9. Experience with RTL simulation, synthesis and back end implementation flows
10. Experience defining and implementing MBIST engines
11. Experience running test compression software
12. Lab and test floor experience with real silicon
13. Experience trading off test options with product performance and schedule requirements

Roles and Responsibilities:
1. Define test structures, debug structures, test plans
2. Create test vectors or oversee their creation
3. Collaborate with physical design team to close requirements
4. Validate DFT requirements are being met
5. Work with designers to increase test coverage, debug observability and flexibility
6. Verify post-PD designs meet DFT requirements
7. Work with test personnel, stepping in to do run tests when needed

GSVR Talent Solutions is full service staffing solutions firm for IT and Engineering that has diligently emerged recruiting and placements. Read more..

Contact:

Phone: +91-6309270075

Email: Info@gsvrtalent.com

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